(1) Field of the Invention
The present invention relates to microprocessor control of main memory and more particularly to direct memory access by a plurality of peripheral devices to the main memory of a microprocessor on a non-priority basis.
(2) Description of the Prior Art
Direct memory access (DMA) to a microprocessor's main memory is a well known technique. Many microprocessors provide a single DMA capability at the integrated circuit level. For example, the INTEL model 8080 central processing unit is a single LSI chip of silicon gate MOS technology with DMA capability. This central processing unit (CPU) provides for a single direct memory access by an associated peripheral device. In addition, a two phase clock is required for its operation.
Upon receipt of a hold request from a peripheral device, the central processing unit suspends its access to the main memory during the initial portion of a machine cycle. The CPU acknowledges the hold request via a hold acknowledge signal returned to the associated peripheral device. The peripheral device now has control of the address bus and data bus for reading or writing memory directly.
Microprocessors, by their nature, are intended for relatively small central processor applications. Usual applications of these processors require only a single peripheral device to be connected for direct memory access. As indicated above, the single peripheral device capacity is inherent in many central processing units.
However, in telecommunications systems where the majority of the central processing unit's real time is utilized, a plurality of direct memory access peripheral devices is required. For example, a telecommunication system may require a magnetic tape cartridge device and a manual programmer's panel to read and write memory directly; or the system may require a plurality of magnetic tape cartridge devices to operate simultaneously.
Therefore, it is the object of the present invention to provide a telecommunication system's microprocessor (such as the INTEL 8080) with the circuit means necessary to control a plurality of peripheral devices simultaneously attempting to access the microprocessor's main memory directly. In addition, it is an objective of the present invention to provide this DMA capability by a plurality of direct memory access peripheral devices in a modular form, so that should the number of peripheral devices required grow, additional access circuits may be added relatively easily to accomplish this result. It is also desirable that the direct memory access unit respond to the connected peripheral devices on a non-priority basis.